As semiconductor technology decreases in size, more devices are being placed on a single die or chip. With so many devices in such close proximity to one another, the importance of insulating the devices from each other becomes paramount in order for the finished product to operate properly and reliably. One method that has been used effectively is the shallow trench isolation (STI). STI fabrication essentially comprises etching shallow trenches in the substrate between the devices and then filling those trenches with an effective insulator. The size and location of the STI provides isolation of devices.
One problem with forming STI between active devices comes from the oxidation that typically occurs in the immediately surround substrate of the STI. This oxidation actually often encroaches on the corners of the device. Because the oxidation essentially makes that portion of the substrate inoperable with the active device, the effective width of the device is geometrically reduced. Transistor current scales with the device width. Therefore, the reduced width caused by the oxidation generally degrades the performance of the active device. As device technology gets smaller and smaller, the effect of this reduced width, especially on narrow-width devices, become more pronounced. However, because the importance of isolating the active devices on the die or chip is paramount, manufacturers generally accept the decreased performance to preserve that isolation.
In the conventional STI approach, the STI liner generally influences the leakage and isolation parameters of the device. During the liner process the active area corner will typically be oxidized and therefore reduced in size, as discussed above. However, during the high temperature anneal process that usually follows the oxide fill and after chemical-mechanical polishing (CMP) the active area typically suffers from further shrinkage. The most common problems of this integration scheme are uniformity issues typically found in the etching, deposition, and polishing processes. Problems such as this will likely be most pronounced in the newer 32 nm technology and beyond.